Multifrequency sequential tone decoder

ABSTRACT

A tone decoder incorporating a plurality of selectable bandpass filters, the frequencies of which are controlled by logic means responsive to the outputs of the filters is presented herein. The logic means are adapted to recognize a plurality of tone bursts having a predetermined duration and repetition rate and provide controlling voltage levels to an active filter providing a selectable one of a plurality of narrow bandpass frequencies in response to the selected voltage levels.

United States Patent Weeks, Jr. et a1.

1451 Jan. 14, 1975 [54] MULTIFREQUENCY SEQUENTIAL TONE 3,238,503 3/1966Uitermark 340/171 PF DECODER 3,766,523 10/1973 Brocker 340/171 PF [76]Inventors: g m w g g tl L tE f E M. Primary Examiner-Harold 1. Pitts 0At: ,A t, F -Edw dJ.1(od k' Flying Cloud Dr., Eden Prairie, omey gen orWm M n me I 55343 57] ABSTRACT [22] Filed: Apr. 13, 1973 A tone decoderincorporating a plurality of selectable bandpass filters, thefrequencies of which are conlz] I Appl' 350925 trolled by logic meansresponsive to the outputs of the filters is presented herein. The logicmeans are [52] US. Cl 340/171 PF, 340/171 R adapted to recognize aplurality of tone bursts having [51] Int. Cl. H04q l/45 a predeterminedduration and repetition rate and pro- [58] Field of Search...'...340/171 PF, 171 R; 325/64 vide controlling voltage levels to an activefilter providing a selectable one of a plurality of narrow band- [56]References Cited pass frequencies in response to the selected voltageUNITED STATES PATENTS levels- 2,811,708 10/1957 Byrnes 340/171 PF 15Claims, 11 Drawing Figures CODE CLOCK SEGMENT CLEAR COUNTERH 1 1 BINARY1 BINARY l BINARY BINARY DECODER DECODER l DECODER DECODER 1s 1 17 i 2021 i 1 END or c001: RESET TIMER 32 1 l i 1 A ON/OFF PROGRAM PROGR M 1 iPLUG 1e 1 PLUG 15 CONTROL 22 AUDIO 1 i 'NPUT ATTENUATOR 1 12 i i i i 1FILTER 14 1 FILTER 13 ON 2 1 0N#l/OFF l A-D CONVERTER 1 A-D CONVERTERRELAY BAND PASS FILTER-i BAND PASS FlLTER mv R 33 FIRST IN DETECTORCONTROL 23 I INTERFACE TO FIG 2B sum 50F 9 A'Flf I I m V W0 u m m v C NW 5 w m R 4 E WE 0L PC I PATENTEU JAN 1 4|975 mm Ea moCSEzT INDICATORCONTROL I03 &

H m 8 m 0 on 2 E PATENTEUJAH 1 M875 SHEET 5 BF 9 TO F|G.3C

l '9 2 (REF.A) u.

I0 I 203 i r- 'CLEAR" FUNCTIONS RESET GATE 20 WAFTEO MULTIFREQUENCYSEQUENTIAL TONE DECODER BACKGROUND OF THE INVENTION A need exists forproviding reliable control signaling utilizing audio tones in abroadcast medium dominated by random audio tones. This need is generatedby the necessity for automatically turning on or off various automatedsystems in response to standard radio and TV audio transmissions. Suchan automated system is described, for example, in US. Pat. No.3,729,581, assigned to the assignee of this invention. The conventionalapproaches to the problem have been to incorporate elaborate decoderswhich constantly moniter audio programs to detect codes comprised ofunique tone burst sequences. These approaches incorporated separate anddistinct bandpass filters for each different frequency of interest.Since the cost of the filters exhibiting acceptable tolerances isrelatively great, the systems cannot be used in average non-commercialapplications due to their total cost considerations.

Because of the various disadvantages associated with existing audio tonedecoders, a need has arisen for a multifrequency sequential tone decoderwhich will provide reliable control signaling utilizing audio tones in abroadcast medium dominated by random audio tones. The required systemmust be relatively maintanence free and highly resistent to erroneousresponses but at the same time it must be relatively economical toproduce. These objectives are accomplished by the invention disclosedherein.

Another objective of this invention is to provide a reliable and stablefilter capable of providing a digital output for a selected frequency,wherein the selected frequency may be changed during the course ofdecodmg.

An additional objective is to provide an apparatus which will berelatively insensitive to background noise and tone bursts which meetbasic tone code criteria but are too short or too long and are actuallyrandom audio tones normally encountered during the course of moniteringa broadcast.

An additional objective is to provide a tone responsive decoder which isresponsive to several codes.

Other objectives, features and advantages of the presented inventionwill become apparent from the following description taken in conjunctionwith the accompanying drawings.

SUMMARY OF THE INVENTION The multifrequency sequential tone decoderpresented by this patent accomplishes the aforestated objectives byproviding a reliable decoder for control signaling utilizing audio tonesin a broadcast medium dominated by random audio tones. The control tonesto which the invention is responsive are broadcast via standard radioand TV audio, and the contemplated use of the system necessitates thatthe decoder constantly monitor program audio signals consisting of toneshaving the same basic makeup as the coded audio control tones.Therefore, the code format must be complex enough to preclude thepossibility of duplication by music, speech, or any other program audionormally encountered, but simple enough to be highly reliable.

The tone deeoder rejects all random audio programming but respondsimmediately when a proper code is received. This is accomplished byusing active, semiconductor bandpass filters which have a high Q and canbe electronically switched to pass different frequencies. They areincorporated in a decoder design which provides electronic switching toenable a single active filter to be responsive to different discretefrequencies in accordance with a timed code.

The transmitted code signals which the system is responsive to consistsof a number of tone bursts, each being made up of one unique discretepure sinusoidal frequency. The frequencies utilized are in the mediumaudio range to enable most home entertainment receiving equipment toeasily accommodate their bandpass. The number of tones that may beutilized by the invention is practically limitless, however, forsimplicity of presentation, the system described is consideredresponsive to 4 tones each of which is considered as an individual digittone. The tones are discrete frequencies which are considered decadedigits, that is 10 different frequencies provide 10 digits.

Each digit tone is transmitted for a predetermined length of time andeach digit frequency is transmitted for the same period of time. Thetransmission is followed by a period of silence which is of a constantduration in all instances. This enables the system to decode the signalby first verifying the frequency of each tone segment, seconddetermining the duration of each tone segment, third determining theexistance of 21 period of silence and forth determining the minimumduration of the period of silence.

The duration of the time checks performed by the system as indicatedabove, is determined by the width of an error sample pulse, which isgenerated by the same timing circuitry, and is of the same duration. Theposition of the error sample pulse within the tone segment is determinedby a tone error sample position timer and the position of the errorsample within the silence segment is determined by a silence errorsample position timer. The tone error sample position timer is initiatedby the first response of the tone filters, while the silence errorsample position timer is initiated at the conclusion of the tone errorsample period. This permits the decoder timer to be asynchronous.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a timing chart illustratingthe time durations utilized in determining the validity of a code.

FIG. 2 is a diagram showing the layout interconnections for FIGS. 2A and2B which when combined present the multifrequency sequential tonedecoder described by this patent.

FIG. 3 is a diagram showing the layout interconnections for FIGS. 3Athrough 3E which combined present a detailed schematic and logic diagramof the multifrequency sequential tone decoder.

FIG. 4 is block diagram of the selectable bandpass filter.

DETAILED DESCRIPTION FIG. 1 illustrates the timing functions utilized bya tone decoder 10 to ascertain the validity of a received code. Thepulse train la represents the code signal received. In the exemplaryembodiment it is a pulse train of four independent tone bursts. The fourtone bursts are decoded by the system which is represented by the blockdiagram presented in FIGS. 2A and 28 as follows. The first received codesignal Tone A, is applied to audio input jack 11 which couples the toneto attenuator 12. The attenuator 12 reduces the amplitude of the inputtone to a minimum level and simultaneously applies it to filters 13 and14. In this embodiment, the system is configured so that filter 13responds to a first ON code and to the OFF code and filter 14 respondsto a second ON code. Additional codes may be accommodated by providingadditional filters in combination with additional binery decoders.However, for simplicity only two filters are illustrated.

Filters 13 and 14 have a very narrow bandpass at a plurality of discreetfrequencies but they pass only one frequency at a time. The frequencythey will pass at a given instant is a function of the voltage levels onthe plurality of inputs from the program plugs 15 and 16, in other wordsbandpass frequency control is provided by program plug 15 for filter 13and by program plug 16 for filter 14. The filters 13 and 14 function asanalog-to-digital converters for the specific frequency to which theyare selectively made responsive to. In their quiescent state theyprovide a logical one output, but upon passing the preselected frequencytheir output changes to a logical zero and will remain at that level aslong as the frequency is present.

In the quiescent state, the code segment counter 17 and binary decoders18, 19, 20 and 21 are in a reset state, and filters 13 and 14 are set torespond to the first digital frequency of the code. This frequency isdetermined by the interconnections provided by the program plugs 15 and16 as previously described.

Considering the exemplary case, the code segment counter 17 and thebinary decoders 18, 19, 20 and 21 are reset and the ON-OFF control 22 isin the OFF position, both filters 13 and 14 are OFF and listening for anON code. When Tone A arrives, filter 13 passes it and applies a logiczero to the first in detector 23 which immediately disables the otherfilter 14. Simultaneously, the logic zero is applied to the tone errorsample position timer24. At the end of a predetermined time, the toneerror sample position timer 24 triggers the error sample duration timer25. After 25 ms, the error sample duration timer 25 switches to itsquiescent state which causes the counter 17 to step one count. When theerror sample duration timer 25 was triggered, it produced a positiveoutput which lasted for 25 ms, as shown in FIG. 1C. This signal wasapplied to both the tone error detector 26 and the silence errordetector 27. However, the tone error detector 26 is the only one whichwill respond to an error at this time because the silence error detector27 is disabled during a tone check; this condition is set by the outputof the first stage of the code segment counter 17 and an inverter.

If the logic zero output of filter 13 stops during this 25 ms period,the tone error detector 26 will generate a reset signal which will lastuntil the end of the 25 ms period. Assuming Tone A is of long enoughduration to persist for the 25 ms test period, the counter 17 steps onecount as stated earlier. When the code segment counter 17 steps aheadone count, the counters 17 output inhibits the tone error detector 26,enables the silence error detector 27 and triggers the silence errorsample position timer 28. At the end of a predeter mined time, thesilence error sample position timer 28 triggers the error sampleduration timer 25. The error sample duration timer 25 produces a 25 mspositive pulse which enables the silence error detector 27 and steps thecounter 17 with its trailing edge.

When the tone was initially received at the audio input jack 11, theattenuated signal output of attenuator 12 was applied to audio amplifier29 which in turn applied its output to sound level detector 30. Soundlevel detector 30 compares the output of audio amplifier 29 with a leveldetermined by threshold level set 31. When the audio signal applied tosound level detector 30 exceeds the threshold set by threshold level set31, it provides a logic zero output. This output is applied to thesilence error detector 27 and if it is present during the duration ofthe silence error sample pulse, illustrated by wave form 1D, FIG. 1, itcauses the silence error detector 27 to generate a reset pulse which hasthe same effect as described for the reset pulse generated by tone errordetector 26.

If the tone is a valid tone, the silence error detector 27 will notreset the counter 17 and it will be stepped one count by the trailingedge of the error pulse output of the sample duration timer 25. The codesegment counter 17 now inhibits the silence error detector 27 andenables the tone error detector 26.

Binary decoder 18 triggers the end of code reset timer 32 which willreset the code segment counter 17 at the end of a predetermined time toprovide functions which will be discussed later.

Binary decoder 19 changes the frequency select control for filters l3and 14. In the examplary case it changes filter 13 to be responsive toTone B. This is a function determined by the wiring of the program plugs15 and 16. Filter 13 is now responsive to the second discrete frequencyof the code.

The previously described sequence repeats itself, as filter 13 respondsto the second tone, the tone error sample position timer 24 determinesthe time at which the error sample duration timer 25 begins the toneerror sample test, by generating an advance pulse signal (as shown inFIG. 1C) whose trailing edge of the pulse steps the code segment counter17 one step to initiate the silence error sample position timer 28 whichdetermines the beginning of the silence segment test. When the codesegment counter 17 advanced one step, the tone error detector 26 wasinhibited and the silence error detector 27 was enabled. If no error isdetected by the silence error detector 27, it steps the code segmentcounter 17 and the filter (13 or 14) is set to respond to Tone C.

As the tones are stepped through the decoder, the error sample for thefinal tone is eventually generated. At the end of that error sample testthe code segment counter 17 is advanced to its capacity. Capacityloading of the code segment counter 17 is detected by binary decoder 21which operates the ON-OFF control 22 to the ON position. When the ON-OFFcontrol 22' is activated to the ON position, it energizes relay driver33 which operates an external relay device. In addition to activatingrelay driver 33, the ON-OFF control 22 disables binary decoders 19 and20 to prevent the filters from responding to any code programmed byeither program 15 or 16 and to therefore respond only to apredetermined, preprogrammed code which is established by the wiringbetween binary decoder 20 and filter 13. This later function is aspecial case for providing a specific OFF code. In general, however, theOFF code may be programmed in a manner similar to that presented for theON code.

Also, additional binary decoders similar to binary decoder 20 may beprovided to allow the use of additional OFF codes. a 1

The end of code reset timer 32 mentioned previously began its timingcycle at the end of the first silence error sample test. It generates areset pulse shortly after the last tone pulse of a given code format.The purpose of the reset timer 32 is to reset the various elements ofthe tone decoder in the event of an incomplete code. For instance, in acase where one or more tone bursts detected by the tone decoder 10correspond to the set codes of the decoder 20, its counter 17 will stepforward until a proper tone burst is not detected by one of the filters13 and 14. In this case, rather than allow the decoder 10 to remain in apartially decoded status, the end of code reset timer 23 will time outand reset the decoder 10.

If the tone detected by the tone decoder 10 is not a valid code, thecode segment counter 17 and first in detector 23 are placed in a resetstate. For instance assume a proper frequency tone burst is detected butthe tone burst is shorter than required. The tone decoder 10 responds tothe frequency of the random signal as if it were the first frequency ofa valid code. This results in the generation of an error sample pulse atthe appropriate time. However, since the duration of the random signalis not long enough, the tone error detector 26 produces an error signalwhich immediately resets the code segment counter 17 and the first indetector 23. This causes filters 13 and 14 to be responsive again to theinitiate first tone of a valid code.

If a random signal equal to the first tone digital fre quency isdetected by the decoder 10 but the tone burst is too long, the first indetector 23 cuts off the opposite filter and a first tone error sampleis generated, found to be satisfactory, and the position of the firstsilence segment error sample is determined. When the error samplingtakes place, the silence error detector 27 will detect the absence ofsilence, and the code segment counter 17 and the first in detector 23will immediately be reset.

If a random tone satisfies a digit frequency requirements but isaccompanied by other frequencies, an error will be generated during thesilence segment checks due to the presence of the other frequencies;

If a random signal is such that the first tone segment and first silenceperiod are verified and considered acceptable, the tone decoder 10 isplaced in a listening mode waiting for the second tone frequency whichwill not be received. In this case the first silence error sample and itgenerated and it causes the end of code reset timer 32 to begin timingout. When the end of code reset timer 32 times out, it resets the codesegment counter 17 and first in detector 23 as previously discribed.

The detailed functioning of the system can best be comprehended byconsidering FIGS. 3A thru 3F which illustrate the total system indetail.

When power is initially applied, the power up clear circuit comprised ofgates 10] and 102 illustrated in FIG. 3 produces a logic zero outputwhich resets indicator control flip-flop 103 and ON-OFF control flipflop104. This signal is also applied to the clear functions reset decoder201 of FIG. 3B which resets the control flip-flop 301 of FIG. 3C, thefirst in detector flip-flop 401 and 402 of FIG. 3B and the code segmentcounter 17 via reset NAND gate 501 of FIG. 3E. De-

coders l9 and 20 of FIG. 3E are reset by outputs from flip-flop 104 atthis time.

Returning to the power-up clear circuit of FIG. 3A, gates 101 and 102are inverted NAND gates so when power is initially applied, one input togate 101 is positive or logic one and the other is logic zero until theRC time circuit 105 charges. Therefore, the initial output of gate 101is zero. The inputs to gate 102 are initially logic one from the powersupply and logic zero from gate 10!. When the RC time constant I05 ischarged, both inputs to gate 101 are positive and the gate produces alogic one which causes gate 102 to produce a logic one since both of itsinputs are now positive. This removes the reset or clear from thevarious circuits previously set and the decoder is ready to processincom ing tones.

When the tone decoder 10 has been reset and is ready to process incomingtones, all the inputs to the clear functions reset gate 201 are at alogic one and since it is an inverted NOR gate its output is a logiczero. NAND gate 501 is at logic zero and the outputs of stages 502, 503and 504 are respectively zero, zero, zero. The logic zero from stage 502is applied to one input of inverted NAND gate 203 of the silence errordetector 27, holding that gate off. The logic zero is also applied to aninverter 505 which applies a logic one to NOR gate 204 of the silenceerror sample position timer 28 to inhibit that circuit and to invertedNAND gate 205 thus enabling the tone error detector 26.

The logic zero from the clear functions reset gate 201 is applied toinverter 206 which applies a logic one to the reset inputs of invertedNOR gate flip-flop 401 and 402 of the first in detectors and invertedNOR gate flipflop 202.

The logic one output of stage 503 is applied to one input of decoder 18which is an inverted NAND gate. The other input to decoder 18 is a logicone from amplifier 506 which inverts the output of stage 504. Thiscauses decoder 18 to produce a logic one which is applied to NOR gate207 to hold the end of code reset timer off.

The output of error sample duration timer 25 is at a logic zero and theoutput of end of code reset timer 32 is at a logic one. a

When no signal or an improper tone is received and the tone decoder 10has been reset as previously described, the output terminals 405 and 406of filters l3 and 14 are at a logic one level. These terminals areconnected to the first in detector flip-flops 402 and 40] respectivelyand to two inputs of control flip-flop 202.

With the logic set as previously described, the decoder is ready toprocess a tone of a frequency to which the filters 13 and 14 are set.

The attenuator 12 of FIG. 3B functions as a limiter as well as anattenuator through the action of diodes 403 and 404. It provides signalshaving a predetermined maximum value to audio amplifier 29 and filtersl3 and 14 of FIG. 3D.

To follow the operation of the decoder, assume a tone is received thatis the same frequency as filter 13:

Output terminal 405 of filter l3 assumes a logic zero level immediatelyand remains at that level as long as the tone persists. The logic zerois sensed by flip-flop 402 and it responds by assuming a logic oneoutput which is applied to inhibit terminal 407 of filter 14. With alogic one at terminal 407, filter 14 is cut-off and will not respond toany tone frequency.

The logic zero at terminal 405 is sensed by control flip-flop 202 ofFIG. 3C causing inverted NOR gate 208 to go to a logic zero which shiftsinverted NOR gate 209 to a logic zero. The logic zero at gate 209 causesNAND gate 210 to assume a logic one and trigger AND gate 211. AND gate211 triggers circuit 212 which provides a 25 ms logic zero pulse toinverted NAND gates 213 and 214. The output of circuit 212 is a logicone in its quiescent state so gates 213 and 214 are normally at a logicone level. When the output of circuit 212 drops to zero, gate 213 assumea logic zero. The discharging of capacitor 215 is prevented fromdelaying this action by resistor 216.

Prior to circuit 212 developing a negative pulse at its Q terminal, theoutput of NAND gate 213 is at a logic zero because both inputs are at alogic one. This logic zero output of 213 ensures that the output of NANDgate 214 is at a logic one even though input A is at a logic one.Immediately, as the one-shot mgnostable circuit, 212, produces a logiczero at output Q, the control of NAND circuit 214 changes from input Bto input A and the output remains at a logic one. The output of NANDgate 214 changes only as the 6 output of circuit 212 changes from alogic zero to a logic one. When this ooccurs, the A input of NAND gate214 immediately changes to a logic one, but the B input does not satisfythe gate until the output of NAND gate 213 switches to a logic one also.This happens at a point in time determined by the RC network consistingof resistor 216 and capacitor 215. The B input of NAND gate 213 exceedsthe positive threshold level only after capacitor 215 changes throughresistor 216. Thus, the output of NAND gate 214 remains unchanged as Qof 212 changes from logic one to logic zero but switches to logic zeroimmediately as Q of 212 returns to logic one; the length of time itcotinues to be a logic zero is determined by the time-constant. Whengate 214 assumes a logic zero. NOR gate 217 assumes a logic one whichtrigers AND gate 218. AND gate 218 sets circuit 219 which is similar tocircuit 212, but the output is taken from the inverted output Q, thusgenerating a logic one.

This change is sensed by NOR gate 217 and it changes to a logic zero,changing the state of AND gate 218 which causes circuit 219 to produce a25 ms logic one pulse at its output terminal.

As shown in FIG. 3E, the logic one is applied to stage 502 of counter 17but this circuit is similar to 219 in that an output is produced only atthe termination of the input pulse so the counter does not step. Thelogic one is also sensed by inverted NAND gate 205 of the tone errordetector 26. This gate now has a logic one input from 219 of errorsample duration timer 25, terminal 406 of filter 14 and NAND gate 505.It is held in the logic one state by the logic zero from terminal 405 offilter 13. If the tone stops while the gate is in this state, it willcause gate 205 to assume a logic zero state, which will cause invertedNOR gate flip-flop 220 to assume a logic zero. This changes the clearfunction reset gate inverted NOR gate to a logic one and the decoder isreset as described for the power-up clear sequence except that the resetlogic levels are held until the logic one of 219 of the error sampleduration timer 25 shifts to a logic zero. Thus the counter 17 isprevented from stepping and the system is again set to receive a tone.

Coincidentally, the logic one of error sample duration timer 25 isapplied to inverted NAND gate 203 of the silence error detector 27 ofFIG. 3B but that gate is held in the logic zero state by the logic zerofrom stage 502- of the code segment counter 17.

Assuming the tone lasted until circuit 219 of the error sample durationtimer 2S shifted to a logic zero, stage 502 is stepped, shifting itsoutput to a logic one. This zero is applied to stage 503 but has noeffect in that the stages of the code segment counter 17 are all similarand only step at the termination of a logic one. The logic one of stage502 is also applied to one input of inverted NAND gate 203 to enable thesilence error detector 27 and to gate 505. This changes gate 505 to alogic zero and inhibits inverted NAND gate 205 of the tone errordetector 26.

The logic zero at the output of gate 505 is sensed by NOR gate 204 ofthe silence error sample position timer 28 of FIG. 3C. This NOR gate 204changes to a logic one and AND gate 221 triggers circuit 222 to operate204 inverted NAND gates 223 and 224 in a fashion identical to thesimilar circuitry of the tone error sample position timer 24 which waspreviously presented. When gate 224 changes to a logic zero, the levelis applied to one input of inverted NOR gate 209 to reset flip-flop 202.This sequence is identical to the sequence which caused circuit 219 toproduce a logic one at its output.

The logic zero of gate 224 is also applied to NOR gate 217 of the errorsample duration timer 25. The

function is similar to that explained for the tone error position timer24 sequence. Hence the error sample position timer developes a 25 mslogic one pulse at the output of circuit 219, 30 MS after the 25 mslogic one pulse developed in response to the tone error sample positiontimer 24 ends.

This logic one pulse is applied to both inverted NAND gates 203 and 205as before, but now gate 203 is enabled by the logic one from stage 502and gate 205 is inhibited by the logic zero from gate 505.

Inverted NAND gate 203 of the silence error detector 27 in a three inputdevice. Two of the inputs are now at a logic one level and the third isprovided by sound level detector 30.

As shown in FIG. 3A, sound level detector 30 is a differential amplifierwhich receives one input from audio amplifier 29. Audio amplifier 29isdriven by the output of attenuator 12, which is the same signal that isapplied to filters 13 and 14. The output of the amplifier is compared bythe sound level detector 30 with a voltage level set by threshold levelset 31 and applied to its negative input. When the audio input to soundlevel detector 30 is less than the threshold level set value, thedetector produces a negative output or a logic zero. When the audio isgreater than the threshold level set value, the detector produces alogic one.

Therefore, if a significant tone is being received, the third input toinverted NAND gate 203 of FIG. 3B is logic one. This causes gate 203 tochange from a logic one to a logic zero and trigger the inverted NORflipflop 225. This changes its output to a logic zero which causes clearfunction reset decoder 201 to shift from a logic zero to a logic one andthe tone decoder 10 is cleared as previously described for the toneerror detector 26.

Assuming the output tone received is proper and therefore ended and noother tone greater than the level set value is present, the output ofthe sound level detector 30 will be a logic zero and gate 203 will notchange state. In this case, when the logic one output of circuit 219ends, it steps stage 502 of the code segment counter 17. The output ofstage 502 goes to a logic zero and steps stage 503 which goes to a logiczero. Stage 504 is not affected for reasons previously discussed withrespect to the first setting of stage 503. The logic zero at 502inhibits gate 203 and enables gate 205 via gate 505 as previouslyexplained with respect to the status of the logic when the decoder iswaiting for a tone. The decoder 10 is ready to repeat the previouslydescribed sequence if a tone arrives. However, the logic zero status ofcode segment counter stage 503 has shifted the inputs to decoders 19 and20.

Initially all eight NAND gates which form decoders 19 and 20 were 3A inat a logic one. This can be determined by inspection of FIG. 3a inconsideration of the logic status of the decoder after the power-upclear cycle as previously presented. Therefore, the unselected controlinput through program plugs and 16 and directly to filter 13 fromdecoder are at a logic one. The diode 408 and resistor 409 to Vcc oneach control input to the filters 13 and 14 cause the actual input to beisolated at a high voltage.

Filter response frequency selection is made by driving a selected oneout of the nine inputs to each filter to a logic zero and the reset to alogic one. Therefore, the initial frequency to which the filters 13 and14 are responsive to is determined by the program plugs.

When code segment counter 17 is cleared to a logic zero output,inverters INV. A and 506 are a logic one which causes control input 410of filter 13 (see FIG. 3D) to be driven to a logic zero, thusestablishing the response frequency of filter 13. Hence the multifrequency tone decoder 10 is now ready to respond to the first toneeither via filter 14 or via filter 13.

When the code segment counter stage 503 shifted to a logic one output,it removed the logic zero from one input to inverted NAND gate 18 andits output went to a logic zero. NOR gate 207 changed state to a logicone and triggered AND gate 226 of the end of code reset timer 32. Thistriggers circuit 227 which remains at a logic zero output for a periodof time slightly longer than required to complete processing the codeand then it goes to a logic one output, and inverted NAND gates 228 and229 produce a momentary logic zero output and clear functions reset gate201 changes to a logic one state and resets the system. Circuit 227 issimilar to circuits 2l2, 2l9 and 222 and functions as a delay circuit atthe Q output.

Decoder NAND gate 21 remains in a logic zero state until the codesegment counter stages 502, 503 and 504 are all stepped to logic oneoutputs, then it shifts to a logic zero and triggers the ON-OFF control22 and the indicator control flip-flop 103 to their ON conditions.

In the embodiment illustrated, when flip-flop 104 is set by decoder 21,it inhibits decoder 19, enables decoder 20 and inhibits filter 14through flip-flop 402. This prevents the system from responding to anycode except the OFF code permanently wired between decoder 20 and filter13. This is a special case however and the system may be made to respondthrough both program plugs at all times.

One of the filters, 13 and 14, which make possible the disclosedmultifrequency sequential tone decoder is illustrated in FIG. 4. Theyare constructed on a thick film R. C. active microcircuit and include aninput amplifier 601 which functions as a limiter squarer and provides aregulated input to the controllable active filter 602. The active filter602 incorporates nine voltage input taps 410 which control the narrowbandpass frequency of the device by providing a current path throughdiodes 408 and resistors 409. When a given input tap is selected,current flow is enabled because the cathode of the diodes 408 is lesspositive than the anode. Hence when a cathode is pulled to ground, logiczero, current flow commences and the portion of the active filterassociated with that particular input or control line is enabled and theresponse frequency changed. The output of the active filter 602 isapplied to a threshold detector 603 which acts as an output buffer. Itprovides a positive output or logic one at terminal 405 as long as theoutput of the active filter 602 is below a preset level. When activefilter 602 exceeds the preset level in response to a valid input tone,the threshold detector 603 is cut-off and the output at terminal 405drops to a logic zero. The module may be used as a digitally controlledoscilator by external strapping.

The actual center frequency of the active filter 602 to any responsefrequency tone is within :10 Hz of the nominal response frequency andthe bandwidth at any given response frequency is no greater than $1.5percent and no less than :1.0 percent of the nominal response frequency.The nominal response frequencies for the active filter 602 is asfollows:

are logic one Response frequency tone selection is made by driving theselected one out of nine control inputs 410 to logic zero whilemaintaining the other eight at logic one as previously explained.However for proper operation the control potential within the activefilter circuit must be greater than 4 volts for logic one and less than0.8 volts for logic zero.

The time between the application of a response frequency tone at theinput 407 of the amplifier 601 and the threshold detector 603 changingfrom a logic one to a logic zero is no greater than 15 milliseconds atany bandpass frequency. The time between the removal of a responsefrequency tone from the input 411 of the amplifier 601 and the thresholddetector 603 changing from a logic zero to a logic one (+5 V) is nogreater than 10 ms.

The active filter 602 responds to any given frequency tone selectedwithin 0.2 ms after the specific control input 410 reaches a logic zerolevel. It becomes unresponsive to any given frequency selected within0.1 ms after the control input 410 reaches a logic one level.

When the latch control line 407 is a logic one the output 405 of thethreshold detector 603 is held at a logic one. This effectively causesthe module to be unresponsive. Once the module has responded to a validsignal of at least millivolts RMS, the output will at no time changestate as long as the input signal remains above the minimum theshold,regardless of amplitude or rate of change of amplitude.

The present embodiment of this invention is to be considered in allrespects as illustrative and not restrictive, the scope of the inventionbeing indicated by the appended claims rather than the foregoingdescription and all changes which come within the meaning and range ofequivalency of the claims therefore are intended to be embraced therein.

What is claimed as a significant advancement to the art for whichLetters Patent are desired is:

l. A multifrequency sequential tone decoder adapted to be responsive toan input tone signal, comprising:

a. a frequency responsive bandpass filter adapted to be selectivelyresponsive to an individual one of a plurality of frequencies, saidfrequency responsive bandpass filter including output means forproviding a logic level output in response to an input tone signal ofsaid selected frequency;

b. sample position means responsive to said logic level output forproviding a first test pulse after a predetermined period of time;

c. tone timing means 26 responsive to said logic level output forproviding a reset signal when said logic level output fails to persist apredetermined period of time;

d. silence position means for providing after a predetermined period oftime after the termination of said first test pulse a second test pulse;

e. silence timing means for providing a reset signal when said inputtone signal exceeds a predetermined amplitude after a predeterminedperiod of time measured from the termination of said first test pulse;and

f. counter means operative in a first mode upon sequential terminationof said first and second test pulses for effecting the switching of saidfrequency responsive bandpass filter to a second one of said pluralityof frequencies and in a second mode in response to any one of said resetsignals for switching said frequency responsive bandpass filter to afirst one of said plurality of frequencies.

2. A multifrequency sequential tone decoder as defined in claim 1,further comprising:

a decoder responsive to said counter means reaching a predeterminedcount for providing an output signal.

3. A multifrequency sequential tone decoder as defined in claim 2,further comprising! an end of code timer for providing a reset signalwhen said counter fails to reach a predetermined count within apredetermined period of time.

4. A multifrequency sequential tone decoder as defined in claim 3,further comprising:

a code selector disposed between said counter and said frequencyresponsive bandpass filter for controlling the sequence of selection ofthe responsive frequencies of said frequency responsive bandpassfilters.

5. A multifrequency sequential tone decoder adapted to be responsive toan input tone signal, comprising:

a plurality of frequency responsive bandpass filters adapted to beselectively responsive to individual ones of a plurality of frequencies,said frequency responsive bandpass filters including output means forproviding logic level outputs in response to an input tone signal ofsaid selected frequency;

b. sample position means responsive to said logic level output forproviding a first test pulse after a predetermined period of time;

c. tone detector means responsive to said logic level output forproviding a reset signal when said logic level output fails to persist apredetermined period of time;

d. silence position means for providing a second test pulse after apredetermined period of time after the termination of said first testpulse;

e. silence detector means for providing a reset signal when said inputtone signal exceeds a predetermined amplitude after a predeterminedperiod of time measured from the termination of said first test pulse;and

f. counter means operative in a first mode upon sequential terminationof said first and second test pulses for switching said frequencyresponsive bandpass filters to second ones of said plurality offrequencies, and in a second mode in response to said reset signals forswitching said frequency responsive bandpass filters to first ones ofsaid plurality of frequencies.

6. A multifrequency sequential tone decoder as defined in claim 5,further comprising:

a detector responsive to said logic level output for inhibiting theoperation of all of said frequency responsive bandpass filters exceptsaid frequency responsive bandpass filter which generated said logiclevel output, and responsive to the termination of said second testpulse for uninhibiting all of said frequency responsive bandpassfilters.

7. A multifrequency sequential tone decoder as defined in claim 6,further comprising:

a decoder responsive to said means reaching a predetermined count forproviding an output signal.

8. A multifrequency sequentail tone decoder as defined in claim 7,further comprising:

an end of code timer for providing upon termination of said second testpulse a reset signal when said counter means fails to reach apredetermined count within a predetermined period of time.

9. A multifrequency sequential tone decoder as defined in claim 8,further comprising:

code selectors disposed between said counter means and said frequencyresponsive bandpass filters for controlling the sequence of selection ofthe responsive frequencies of said frequency responsive bandpassfilters.

10. A multifrequency sequential tone decoder adapted to be responsive toan input tone signal, comprising:

A. a plurality of frequency responsive bandpass filters adapted to beselectively responsive to individual ones of a plurality of frequencies,said frequency responsive bandpass filters including output means forproviding logic level outputs in response to an input of said selectedfrequency;

b. detector means responsive to said logic level output for inhibitingthe operation of all of said frequency responsive bandpass filtersexcept said frequency responsive bandpass filter which generated saidlogic level output;

0. sample position means responsive to said logic level output forproviding a first test pulse after a predetermined period of time;

d. tone detector means responsive to said logic level output forproviding a reset signal when said logic level output fails to persistuntil the termination of said first test pulse; e. silence positionmeans for providing a second test pulse after a predetermined period oftime measured from the termination of said first test pulse;

f. silence detector means for providing a reset signal when said inputtone signal exceeds a predetermined amplitude after a predeterminedperiod of time measured from the termination of said first test pulse;

g. a counter means operative in a first mode upon sequential terminationof said first and second test pulses for providing in sequence aplurality of coded outputs, and in a second mode for providing the firstcoded output of said plurality in response to said reset signal;

code selectors responsive to said plurality of coded outputs forswitching said frequency responsive bandpass filters to predeterminedones of said plurality of frequencies;

. decoder means responsive to said counter reaching a predeterminedcount for providing an output signal;

j. said counter means responsive to said reset signal for actuating saiddetector to uninhibit the operation of all of said inhibited frequencyresponsive bandpass filters; and

k. an end of code timer for providing upon the occurrence of thetermination of said second test pulse a reset signal when said countermeans fails to reach a predetermined count within a predetermined periodof time.

11. A multifrequency sequential tone decoder for identifying an inputsignal having an address portion comprised of a tone burst of selectedfrequency and first predetermined duration followed by a blank portionof relatively lower amplitude and second predetermined duration, saiddecoder comprising:

a. filter means coupled to receive the input signal and selectivelycontrollable to respond to one of a plurality of frequencies to providean output signal indicative of the selected one frequency;

b. duration timer means for providing a first output signalcorresponding to one of said predetermined durations after theoccurrence of the output signal of said filter means;

c. burst timing means responsive to the output signals of said durationtimer means and said filter means for providing a reset signal if saidoutput of said filter means does not last for the first predeterminedduration;

d. counter means operative in a first mode for effecting the operationof said filter means to be responsive to another one of said pluralityof frequencies, and in a second mode in response to the reset signal foreffecting the operation of said filter means to be responsive to a firstone of said plurality of frequencies; e. said duration timer means forproviding a second output signal corresponding to the second durationupon a change of said counter means from its first to its second mode ofoperation, said counter means responsive to the second output signal ofsaid duration timer means to be disposed in its first mode of operation;and

f. blank timing means responsive to the second output signal of saidduration timer means for generating a reset signal to be applied to saidcounter means when the input signal exceeds the relatively lowamplitude.

12. The tone decoder as claimed in claim 11, wherein there is furtherincluded programmable decoder means responsive to the count output ofsaid counter means for selectively controlling the one frequency towhich said filter means is responsive as the count output of saidcounter means advances in response to the output signals of saidduration timer means.

13. The tone decoder as claimed in claim 11, wherein there is furtherincluded at least second filter means selectively controllable to beresponsive to one of a plurality of frequencies to provide an outputsignal indicative of the selected one frequency; and detector meansresponsive to the output of one of said first-mentioned and secondfilter means for actuating the other of said filter means to respond toits one frequency and for deactuating said one filter means.

14. The tone decoder as claimed in claim 1 1, wherein said burst timingmeans is deactuated when said counter means is operative in its secondmode, and said blank timing means is deactuated when said counter meansis operative in its first mode.

15. The tone decoder as claimed in claim 11, wherein there is furtherincluded amplitude detecting means responsive to the input signal forproviding an output indicative of an input signal exceeding therelatively lower amplitude, and said blank timing means responsive tothe output of said amplitude detecting means and the second outputsignal of said duration timer means for generating a reset signal.

1. A multifrequency sequential tone decoder adapted to be responsive toan inpuT tone signal, comprising: a. a frequency responsive bandpassfilter adapted to be selectively responsive to an individual one of aplurality of frequencies, said frequency responsive bandpass filterincluding output means for providing a logic level output in response toan input tone signal of said selected frequency; b. sample positionmeans responsive to said logic level output for providing a first testpulse after a predetermined period of time; c. tone timing means 26responsive to said logic level output for providing a reset signal whensaid logic level output fails to persist a predetermined period of time;d. silence position means for providing after a predetermined period oftime after the termination of said first test pulse a second test pulse;e. silence timing means for providing a reset signal when said inputtone signal exceeds a predetermined amplitude after a predeterminedperiod of time measured from the termination of said first test pulse;and f. counter means operative in a first mode upon sequentialtermination of said first and second test pulses for effecting theswitching of said frequency responsive bandpass filter to a second oneof said plurality of frequencies and in a second mode in response to anyone of said reset signals for switching said frequency responsivebandpass filter to a first one of said plurality of frequencies.
 2. Amultifrequency sequential tone decoder as defined in claim 1, furthercomprising: a decoder responsive to said counter means reaching apredetermined count for providing an output signal.
 3. A multifrequencysequential tone decoder as defined in claim 2, further comprising: anend of code timer for providing a reset signal when said counter failsto reach a predetermined count within a predetermined period of time. 4.A multifrequency sequential tone decoder as defined in claim 3, furthercomprising: a code selector disposed between said counter and saidfrequency responsive bandpass filter for controlling the sequence ofselection of the responsive frequencies of said frequency responsivebandpass filters.
 5. A multifrequency sequential tone decoder adapted tobe responsive to an input tone signal, comprising: a plurality offrequency responsive bandpass filters adapted to be selectivelyresponsive to individual ones of a plurality of frequencies, saidfrequency responsive bandpass filters including output means forproviding logic level outputs in response to an input tone signal ofsaid selected frequency; b. sample position means responsive to saidlogic level output for providing a first test pulse after apredetermined period of time; c. tone detector means responsive to saidlogic level output for providing a reset signal when said logic leveloutput fails to persist a predetermined period of time; d. silenceposition means for providing a second test pulse after a predeterminedperiod of time after the termination of said first test pulse; e.silence detector means for providing a reset signal when said input tonesignal exceeds a predetermined amplitude after a predetermined period oftime measured from the termination of said first test pulse; and f.counter means operative in a first mode upon sequential termination ofsaid first and second test pulses for switching said frequencyresponsive bandpass filters to second ones of said plurality offrequencies, and in a second mode in response to said reset signals forswitching said frequency responsive bandpass filters to first ones ofsaid plurality of frequencies.
 6. A multifrequency sequential tonedecoder as defined in claim 5, further comprising: a detector responsiveto said logic level output for inhibiting the operation of all of saidfrequency responsive bandpass filters except said frequency responsivebandpass filter which generated said logic level output, and responsiveto the termination of said second test pulse for uninhibiting all ofsaid frequenCy responsive bandpass filters.
 7. A multifrequencysequential tone decoder as defined in claim 6, further comprising: adecoder responsive to said means reaching a predetermined count forproviding an output signal.
 8. A multifrequency sequentail tone decoderas defined in claim 7, further comprising: an end of code timer forproviding upon termination of said second test pulse a reset signal whensaid counter means fails to reach a predetermined count within apredetermined period of time.
 9. A multifrequency sequential tonedecoder as defined in claim 8, further comprising: code selectorsdisposed between said counter means and said frequency responsivebandpass filters for controlling the sequence of selection of theresponsive frequencies of said frequency responsive bandpass filters.10. A multifrequency sequential tone decoder adapted to be responsive toan input tone signal, comprising: A. a plurality of frequency responsivebandpass filters adapted to be selectively responsive to individual onesof a plurality of frequencies, said frequency responsive bandpassfilters including output means for providing logic level outputs inresponse to an input of said selected frequency; b. detector meansresponsive to said logic level output for inhibiting the operation ofall of said frequency responsive bandpass filters except said frequencyresponsive bandpass filter which generated said logic level output; c.sample position means responsive to said logic level output forproviding a first test pulse after a predetermined period of time; d.tone detector means responsive to said logic level output for providinga reset signal when said logic level output fails to persist until thetermination of said first test pulse; e. silence position means forproviding a second test pulse after a predetermined period of timemeasured from the termination of said first test pulse; f. silencedetector means for providing a reset signal when said input tone signalexceeds a predetermined amplitude after a predetermined period of timemeasured from the termination of said first test pulse; g. a countermeans operative in a first mode upon sequential termination of saidfirst and second test pulses for providing in sequence a plurality ofcoded outputs, and in a second mode for providing the first coded outputof said plurality in response to said reset signal; h. code selectorsresponsive to said plurality of coded outputs for switching saidfrequency responsive bandpass filters to predetermined ones of saidplurality of frequencies; i. decoder means responsive to said counterreaching a predetermined count for providing an output signal; j. saidcounter means responsive to said reset signal for actuating saiddetector to uninhibit the operation of all of said inhibited frequencyresponsive bandpass filters; and k. an end of code timer for providingupon the occurrence of the termination of said second test pulse a resetsignal when said counter means fails to reach a predetermined countwithin a predetermined period of time.
 11. A multifrequency sequentialtone decoder for identifying an input signal having an address portioncomprised of a tone burst of selected frequency and first predeterminedduration followed by a blank portion of relatively lower amplitude andsecond predetermined duration, said decoder comprising: a. filter meanscoupled to receive the input signal and selectively controllable torespond to one of a plurality of frequencies to provide an output signalindicative of the selected one frequency; b. duration timer means forproviding a firt output signal corresponding to one of saidpredetermined durations after the occurrence of the output signal ofsaid filter means; c. burst timing means responsive to the outputsignals of said duration timer means and said filter means for providinga reset signal if said output of said filter means does not last for thefirst prEdetermined duration; d. counter means operative in a first modefor effecting the operation of said filter means to be responsive toanother one of said plurality of frequencies, and in a second mode inresponse to the reset signal for effecting the operation of said filtermeans to be responsive to a first one of said plurality of frequencies;e. said duration timer means for providing a second output signalcorresponding to the second duration upon a change of said counter meansfrom its first to its second mode of operation, said counter meansresponsive to the second output signal of said duration timer means tobe disposed in its first mode of operation; and f. blank timing meansresponsive to the second output signal of said duration timer means forgenerating a reset signal to be applied to said counter means when theinput signal exceeds the relatively low amplitude.
 12. The tone decoderas claimed in claim 11, wherein there is further included programmabledecoder means responsive to the count output of said counter means forselectively controlling the one frequency to which said filter means isresponsive as the count output of said counter means advances inresponse to the output signals of said duration timer means.
 13. Thetone decoder as claimed in claim 11, wherein there is further includedat least second filter means selectively controllable to be responsiveto one of a plurality of frequencies to provide an output signalindicative of the selected one frequency; and detector means responsiveto the output of one of said first-mentioned and second filter means foractuating the other of said filter means to respond to its one frequencyand for deactuating said one filter means.
 14. The tone decoder asclaimed in claim 11, wherein said burst timing means is deactuated whensaid counter means is operative in its second mode, and said blanktiming means is deactuated when said counter means is operative in itsfirst mode.
 15. The tone decoder as claimed in claim 11, wherein thereis further included amplitude detecting means responsive to the inputsignal for providing an output indicative of an input signal exceedingthe relatively lower amplitude, and said blank timing means responsiveto the output of said amplitude detecting means and the second outputsignal of said duration timer means for generating a reset signal.